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general description the max9242/max9244/max9246/max9254 deserialize three lvds serial-data inputs into 21 single-ended lvc- mos/lvttl outputs. a separate parallel-rate lvds clock provides the timing for deserialization. the max9242/ max9244/max9246/max9254 feature spread-spectrum capability, allowing the output data and clock frequency to spread over a specified range to reduce emi. the sin- gle-ended data and clock outputs are programmable for a frequency spread of ?%, ?%, or no spread. the spread-spectrum function is also available when the max9242/max9244/max9246/max9254 operate in non- dc-balanced mode. the modulation rate of the spread is 32khz for a 33mhz lvds clock input and scales linearly with frequency. the single-ended outputs have a sepa- rate supply, allowing +1.8v to +5v output logic levels. the max9254 features high output drive current for both data and clock outputs for faster transition times in the presence of heavy capacitive loads. the max9242/max9244/max9246/max9254 feature pro- grammable dc balance, allowing isolation between a serializer and deserializer using ac-coupling. the max9242/max9244/max9246/max9254 operate with the max9209/max9213 serializers and are available with a rising-edge strobe (max9242) or falling-edge strobe (max9244/max9246/max9254). the lvds inputs meet iso 10605 esd specifications with ?0kv air-gap discharge and ?kv contact discharge ratings. applications automotive navigation systems automotive dvd entertainment systems digital copiers laser printers features ? programmable 4%, 2%, or off spread-spectrum output for reduced emi ? programmable dc-balanced or non-dc-balanced modes ? dc balance allows ac-coupling for wider input common-mode voltage range ? spread spectrum operates in dc-balanced or non-dc-balanced mode ? high output drive (max9254) ? / 4 deskew by oversampling (max9242/max9244/max9254) ? 16mhz-to-34mhz (dc-balanced) and 20mhz-to- 40mhz (non-dc-balanced) operation (max9242/max9244/max9254) ? 6mhz-to-18mhz (dc-balanced) and 8mhz-to-20mhz (non-dc-balanced) operation (max9246) ? rising-edge (max9242) or falling-edge (max9244/max9246/max9254) output strobe ? high-impedance outputs when pwrdwn is low allow output busing ? separate output supply allows interface to +1.8v, +2.5v, +3.3v, and +5v logic ? lvds inputs meet iso 10605 esd protection at 30kv air-gap discharge and 6kv contact discharge ? lvds inputs meet iec 61000-4-2 level 4 esd protection at 15kv air-gap discharge and 8kv contact discharge ? lvds inputs conform to ansi tia/eia-644 standard ? +3.3v main power supply max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance ________________________________________________________________ maxim integrated products 1 ordering information 19-3954; rev 4; 7/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max9242 eum -40? to +85? 48 tssop MAX9242EUM/v+ -40? to +85? 48 tssop max9242gum -40? to +105? 48 tssop max9242gum/v+ -40? to +105? 48 tssop max9244 eum -40? to +85? 48 tssop max9244eum/v+ -40? to +85? 48 tssop max9244gum -40? to +105? 48 tssop max9244gum/v+ -40? to +105? 48 tssop + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. note: all devices are available in lead(pb)-free/rohs-compliant packaging. specify lead(pb)-free/rohs compliant by adding a + symbol at the end of the part number when ordering. selector guide frequency range part strobe edge over- sampling non-dc balance (mhz) dc balance (mhz) max9242 rising yes 20 to 40 16 to 34 max9244 falling yes 20 to 40 16 to 34 max9246 falling no 8 to 20 6 to 18 max9254 falling yes 20 to 40 16 to 34 pin configuration appears at end of data sheet. ordering information continued at end of data sheet. evaluation kit available
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = lvdsv cc = pllv cc = +3.0v to +3.6v, v cco = +3.0v to +5.5v, pwrdwn = high; ssg = high, open, or low; dcb = high or low, differential input voltage |v id | = 0.05v to 1.2v, input common-mode voltage v cm = |v id / 2| to 2.4v - |v id / 2|, unless otherwise noted. typical values are at v cc = v cco = lvdsv cc = pllv cc = +3.3v, |v id | = 0.2v, v cm = +1.25v, t a = +25?.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) v cc , lvdsv cc , pllv cc .......................................-0.5v to +4.0v v cco ......................................................................-0.5v to +6.0v rxin__, rxclkin_.................................................-0.5v to +4.0v pwrdwn ..............................................................-0.5v to +6.0v ssg, dcb...................................................-0.5v to (v cc + 0.5v) rxout_, rxclkout ...............................-0.5v to (v cco + 0.5v) continuous power dissipation (t a = +70?) 48-pin tssop (derate 16mw/? above +70?) ........1282mw esd protection human body model (r d = 1.5k , c s = 100pf) all pins to gnd .............................................................?.5kv iec 61000-4-2 (r d = 330 , c s = 150pf) lvds inputs to gnd (air-gap discharge).....................?5kv lvds inputs to gnd (contact discharge).......................?kv iso 10605 (r d = 2.0k , c s = 330pf) lvds inputs to gnd (air-gap discharge).....................?0kv lvds inputs to gnd (contact discharge).......................?kv operating temperature range .........................-40? to +105? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units power supply power-supply range v cc , lvdsv cc , pllv cc 3.0 3.6 v output-supply range v cco 1.8 5.5 v 16mhz 50 68 dc-balanced mode (ssg = low) 34mhz 81 108 20mhz 55 73 33mhz 75 97 non-dc-balanced mode (ssg = low) 40mhz 83 110 16mhz 62 85 d c - b al anced m od e ( s sg = hi g h or op en) 34mhz 101 135 20mhz 67 91 33mhz 93 123 worst-case supply current i ccw c l = 8pf, worst-case pattern, v cc = v cco = 3.0v to 3.6v, figure 2 (max9242, max9244, max9254) n on- d c -b al anced m ode ( s sg = hi g h or op en) 40mhz 107 134 ma
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = lvdsv cc = pllv cc = +3.0v to +3.6v, v cco = +3.0v to +5.5v, pwrdwn = high; ssg = high, open, or low; dcb = high or low, differential input voltage |v id | = 0.05v to 1.2v, input common-mode voltage v cm = |v id / 2| to 2.4v - |v id / 2|, unless otherwise noted. typical values are at v cc = v cco = lvdsv cc = pllv cc = +3.3v, |v id | = 0.2v, v cm = +1.25v, t a = +25?.) (notes 1, 2) parameter symbol conditions min typ max units 6mhz 29 45 8mhz 33 49 dc-balanced mode (ssg = low) 18mhz 48 69 8mhz 33 47 10mhz 37 52 non-dc-balanced mode (ssg = low) 20mhz 52 73 6mhz 37 54 8mhz 41 62 d c -b al anced m od e ( s sg = hi g h or op en) 18mhz 65 91 8mhz 41 58 10mhz 46 65 worst-case supply current i ccw c l = 8pf, worst-case pattern, v cc = v cco = 3.0v to 3.6v, figure 2 (max9246) n on- d c -b al anced m ode ( s sg = hi g h or op en) 20mhz 66 92 ma power-down supply current i ccz pwrdwn = low 50 ? 5v-tolerant logic input ( pwrdwn ) high-level input voltage v ih 2.0 5.5 v low-level input voltage v il -0.3 +0.8 v input current i in pwrdwn = high or low level -20 +20 ? input clamp voltage v cl i cl = -18ma -1.5 v three-level logic inputs (dcb, ssg) high-level input voltage v ih 2.5 v cc + 0.3 v mid-level input current i im d c b, s s g op en or connected to a d r i ver w i th outp ut i n hi g h- i m p ed ance state ( n ote 3) -10 +10 ? low-level input voltage v il -0.3 +0.8 v input current i in dcb, ssg = high or low level, pwrdwn = high or low -20 +20 ? input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs (rxout_, rxclkout) i oh = -100? v cco - 0.1 rxclkout (note 4) v cco - 0.25 v cco - 0.43 high-level output voltage v oh i oh = -2ma rxout_ max9254 v cco - 0.25 v i ol = 100? 0.1 rxclkout (note 4) 0.2 0.26 low-level output voltage v ol i ol = 2ma rxout_ max9254 0.2 v
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance 4 _______________________________________________________________________________________ ac electrical characteristics (v cc = lvdsv cc = pllv cc = +3.0v to +3.6v, v cco = +3.0v to +3.6v, c l = 8pf, pwrdwn = high; ssg = high, open, or low; dcb = high or low, differential input voltage |v id | = 0.1v to 1.2v, input common-mode voltage v cm = |v id / 2| to 2.4v - |v id / 2|, unless otherwise noted. typical values are at v cc = v cco = lvdsv cc = pllv cc = +3.3v, |v id | = 0.2v, v cm = +1.25v, t a = +25?.) (notes 6, 7, 8) parameter symbol conditions min typ max units rxout_ 2.9 4.7 6.5 output rise time clht 0.1 x v c c o to 0.9 x v c c o , fi g ur e 3 rxclkout 2.0 3.3 4.1 ns rxout_ 2.1 3.0 4.2 output fall time chlt 0.9 x v c c o to 0.1 x v c c o , fi g ur e 3 rxclkout 1.10 1.94 2.70 ns output rise time (max9254) clht 0.1 x v c c o to 0.9 x v c c o , fi g ur e 3 rxout_ 1.4 2.2 3.3 ns output fall time (max9254) chlt 0.9 x v c c o to 0.1 x v c c o , fi g ur e 3 rxclkout 1.1 1.8 2.8 ns 16mhz 2560 3142 dc-balanced mode, figure 4 34mhz 900 1386 20mhz 2500 3164 rxin__ skew margin (note 9) rskm non-dc-balanced mode, figure 4 40mhz 960 1371 ps dc electrical characteristics (continued) (v cc = lvdsv cc = pllv cc = +3.0v to +3.6v, v cco = +3.0v to +5.5v, pwrdwn = high; ssg = high, open, or low; dcb = high or low, differential input voltage |v id | = 0.05v to 1.2v, input common-mode voltage v cm = |v id / 2| to 2.4v - |v id / 2|, unless otherwise noted. typical values are at v cc = v cco = lvdsv cc = pllv cc = +3.3v, |v id | = 0.2v, v cm = +1.25v, t a = +25?.) (notes 1, 2) parameter symbol conditions min typ max units high-impedance output current i oz pwrdwn = low, v out = -0.3v to (v cco + 0.3v) -30 +30 ? rxclkout (note 4) -10 -40 v cco = 3.0v to 3.6v, v out = 0v rxout_ -5 -20 rxclkout (note 4) -28 -75 output short-circuit current (note 5) i os v cco = 4.5v to 5.5v, v out = 0v rxout_ -13 -37 ma rxout_ v cco = 3.0v to 3.6v, v out = 0v rxclkout (note 4) -16 -51 rxout_ output short-circuit current (max9254) (note 5) i os v cco = 4.5v to 5.5v, v out = 0v rxclkout (note 4) -34 -93 ma lvds inputs (rxin__, rxclkin_) differential input high threshold v th (note 6) 50 mv differential input low threshold v tl (note 6) -50 mv input current i in+ , i in- pwrdwn = high or low -25 +25 ? power-off input current i ino+ , i ino- v cc = v cco = 0v or open -40 +40 ? -40? to +85? 42 78 input resistor 1 r in1 pwrdwn = high or low, v cc = v cco = 0v or open, figure 1 -40? to +105? 42 85 k -40? to +85? 246 410 input resistor 2 r in2 pwrdwn = high or low, v cc = v cco = 0v or open, figure 1 -40? to +105? 246 440 k
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance _______________________________________________________________________________________ 5 note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to ground, except v th and v tl . note 2: maximum and minimum limits over temperature are guaranteed by design and characterization. devices are production tested at t a = +25?. note 3: to provide a mid level, leave the input open, or, if driven, put driver in high impedance. high-impedance leakage current must be less than ?0?. note 4: rxclkout limits are scaled based on rxout_ measurements, design, and characterization data. note 5: one output shorted at a time. current out of the pin. note 6: v th , v tl , and ac parameters are guaranteed by design and characterization, and are not production tested. limits are set at ? sigma. note 7: c l includes probe and test jig capacitance. note 8: rcip is the period of rxclkin_. rcop is the period of rxclkout. note 9: rskm is measured with less than 150ps cycle-to-cycle jitter on rxclkin_. ac electrical characteristics (continued) (v cc = lvdsv cc = pllv cc = +3.0v to +3.6v, v cco = +3.0v to +3.6v, c l = 8pf, pwrdwn = high; ssg = high, open, or low; dcb = high or low, differential input voltage |v id | = 0.1v to 1.2v, input common-mode voltage v cm = |v id / 2| to 2.4v - |v id / 2|, unless otherwise noted. typical values are at v cc = v cco = lvdsv cc = pllv cc = +3.3v, |v id | = 0.2v, v cm = +1.25v, t a = +25?.) (notes 6, 7, 8) parameter symbol conditions min typ max units rxclkout high time rcoh figures 5a, 5b 0.35 x rcop ns rxclkout low time rcol figures 5a, 5b 0.35 x rcop ns rxout_ setup to rxclkout rsrc figures 5a, 5b 0.3 x rcop ns rxout_ hold from rxclkout rhrc figures 5a, 5b 0.45 x rcop ns rxclkin_ to rxclkout delay rccd ssg = low, figures 6a, 6b 4.5 + (rcip / 2) 6.5 + (rcip / 2) 8.2 + (rcip / 2) ns deserializer phase-locked- loop set rplls figure 7 65,600 x rcip ns deserializer power-down delay rpdd figure 8 100 ns deserializer phase-locked- loop set from ssg change rplls2 figure 9 32,800 x rcip ns m axi m um outp ut fr eq uency f rxclkin_ + 3.6% f rxclkin_ + 4.0% f rxclkin_ + 4.4% ssg = high, figure 10 minimum output frequency f rxclkin_ - 4.4% f rxclkin_ - 4.0% f rxclkin_ - 3.6% m axi m um outp ut fr eq uency f rxclkin_ + 1.8% f rxclkin_ + 2.0% f rxclkin_ + 2.2% ssg = open, figure 10 minimum output frequency f rxclkin_ - 2.2% f rxclkin_ - 2.0% f rxclkin_ - 1.8% spread-spectrum output frequency f rxclkout ssg = low f rxclkin_ f rxclkin_ mhz spread-spectrum modulation frequency f ssm figure 10 f rxclkin_ / 1016 hz
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance 6 _______________________________________________________________________________________ test circuits/timing diagrams v cc - 0.3v v cc r in2 r in1 rxin_ + or rxclkin+ rxin_ - or rxclkin- r in1 r in1 rxin_ + or rxclkin+ rxin_ - or rxclkin- r in1 fail-safe comparator dc-balanced mode non-dc-balanced mode 1.2v figure 1. lvds input circuits rcop rxclkout odd rxout even rxout figure 2. worst-case test pattern 90% 90% 10% 10% chlt clht rxout_ or rxclkout rxout_ or rxclkout 8pf figure 3. output load and transition times ideal min max internal strobe ideal rskm rskm ideal serial bit time 1.3v 1.1v figure 4. lvds receiver input skew margin rxout_ rxclk out rcop rcoh rcol 2.0v 0.8v 2.0v 0.8v 2.0v 2.0v 2.0v 0.8v 0.8v rhrc rsrc figure 5a. rising-edge output setup/hold and high/low times
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance _______________________________________________________________________________________ 7 test circuits/timing diagrams (continued) v id = 0v 1.5v rccd rxclkin_ rxclkout rcip figure 6a. clock-in to clock-out delay (max9244/max9246/ max9254) v cc rxclkin_ rxclkout pwrdwn 3v 2v rplls high impedance 1.5v figure 7. phase-locked-loop set time 1.5v pwrdwn rxclkin_ rxout_ rxclkout rpdd high impedance 1.5v figure 8. power-down delay rxclkin_ rxclkout + - rccd 1.5v v id = 0v rcip figure 6b. clock-in to clock-out delay (max9242) rxout_ rxclkout rcop rcoh rcol 2.0v 0.8v 2.0v 0.8v 2.0v 2.0v 0.8v 0.8v 0.8v rhrc rsrc figure 5b. falling-edge output setup/hold and high/low times
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance 8 _______________________________________________________________________________________ test circuits/timing diagrams (continued) frequency time f rxclkout (max) f rxclkin_ f rxclkout (min) 1 / f ssm figure 10. simplified modulation profile rxclkout ssg open or less than 10 a leakage 2.5v 0.8v rxclkin_ rxout_ rplls2 timing shown for falling-edge strobe (max9244/max9246/max9254) pwrdwn = high figure 9. phase-locked-loop set time from ssg change
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance _______________________________________________________________________________________ 9 worst-case and prbs supply current vs. frequency (non-dc-balanced mode, no spread) max9242 toc01 frequency (mhz) supply current (ma) 35 30 25 20 40 50 60 70 80 90 100 30 15 40 worst-case pattern 2 7 - 1 prbs worst-case and prbs supply current vs. frequency (dc-balanced mode, no spread) max9242 toc02 frequency (mhz) supply current (ma) 35 30 25 20 40 50 60 70 80 90 100 30 15 40 worst-case pattern 2 7 - 1 prbs worst-case and prbs supply current vs. frequency (dc-balanced mode, 2% spread) max9242 toc03 frequency (mhz) supply current (ma) 35 30 25 20 40 50 60 70 80 90 100 30 15 40 worst-case pattern 2 7 - 1 prbs worst-case and prbs supply current vs. frequency (dc-balanced mode, 4% spread) max9242 toc04 frequency (mhz) supply current (ma) 35 30 25 20 40 50 60 70 80 90 100 30 15 40 worst-case pattern 2 7 - 1 prbs rxout_ output loading max9242 toc05 load (ma) dropout (v) 2 1 2.9 3.0 3.1 3.2 3.3 3.4 2.8 03 max9254 max9244 typical operating characteristics (v cc = pllv cc = lvdsv cc = v cco = +3.3v, c l = 8pf, pwrdwn = high, differential input voltage |v id | = 0.2v, input common-mode voltage v cm = 1.2v, t a = +25?, max9244/max9254, unless otherwise noted.) rxout_transition time vs. output supply voltage (v cco ) max9242 toc06 output supply voltage (v) output transition time (ns) 3.5 3.0 2.5 2.0 2 4 6 8 10 12 14 0 1.5 4.0 5.0 4.5 5.5 c lht c hlt rxclkout power spectrum vs. frequency (rxclkin_ = 33mhz, no spread) max9242 toc07 frequency (mhz) power spectrum (dbm) 33 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 30 36 resolution bw = 100khz video bw = 100khz attenuation = 50db rxclkout power spectrum vs. frequency (rxclkin_ = 33mhz, 2% spread) max9242 toc08 frequency (mhz) power spectrum (dbm) 33 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 30 36 resolution bw = 100khz video bw = 100khz attenuation = 50db rxclkout power spectrum vs. frequency (rxclkin_ = 33mhz, 4% spread) max9242 toc09 frequency (mhz) power spectrum (dbm) 33 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 30 36 resolution bw = 100khz video bw = 100khz attenuation = 50db
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance 10 ______________________________________________________________________________________ typical operating characteristics (continued) (v cc = pllv cc = lvdsv cc = v cco = +3.3v, c l = 8pf, pwrdwn = high, differential input voltage |v id | = 0.2v, input common-mode voltage v cm = 1.2v, t a = +25?, max9244/max9254, unless otherwise noted.) rxclkout power spectrum vs. frequency (rxclkin_ = 16mhz, no spread) max9242 toc10 frequency (mhz) power spectrum (dbm) 16 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 14 18 resolution bw = 100khz video bw = 100khz attenuation = 50db rxclkout power spectrum vs. frequency (rxclkin_ = 16mhz, 2% spread) max9242 toc11 frequency (mhz) power spectrum (dbm) 16 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 14 18 resolution bw = 100khz video bw = 100khz attenuation = 50db rxclkout power spectrum vs. frequency (rxclkin_ = 16mhz, 4% spread) max9242 toc12 frequency (mhz) power spectrum (dbm) 16 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 14 18 resolution bw = 100khz video bw = 100khz attenuation = 50db rxout_ power spectrum vs. frequency (rxclkin_ = 33mhz, no spread) max9242 toc13 frequency (mhz) power spectrum (dbm) 16.5 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 15.0 18.0 resolution bw = 100khz video bw = 100khz attenuation = 50db rxout_ power spectrum vs. frequency (rxclkin_ = 33mhz, 2% spread) max9242 toc14 frequency (mhz) power spectrum (dbm) 16.5 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 15.0 18.0 resolution bw = 100khz video bw = 100khz attenuation = 50db rxout_ power spectrum vs. frequency (rxclkin_ = 33mhz, 4% spread) max9242 toc15 frequency (mhz) power spectrum (dbm) 16.5 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 15.0 18.0 resolution bw = 100khz video bw = 100khz attenuation = 50db rxout_ power spectrum vs. frequency (rxclkin_ = 16mhz, no spread) max9242 toc16 frequency (mhz) power spectrum (dbm) 8 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 79 resolution bw = 100khz video bw = 100khz attenuation = 50db rxout_ power spectrum vs. frequency (rxclkin_ = 16mhz, 2% spread) max9242 toc17 frequency (mhz) power spectrum (dbm) 8 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 79 resolution bw = 100khz video bw = 100khz attenuation = 50db rxout_ power spectrum vs. frequency (rxclkin_ = 16mhz, 4% spread) max9242 toc18 frequency (mhz) power spectrum (dbm) 8 -40 -30 -20 -10 0 10 20 -50 -70 -60 -80 79 resolution bw = 100khz video bw = 100khz attenuation = 50db
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance ______________________________________________________________________________________ 11 pin description pin name function 1 rxout17 2 rxout18 channel 2 single-ended outputs 3, 25, 32, 38, 44 gnd ground 4 rxout19 5 rxout20 channel 2 single-ended outputs 6 ssg three-level-logic, spread-spectrum generator control input. ssg selects the frequency spread of rxclkout relative to rxclkin_ (see table 3). 7 dcb three-level-logic, dc-balance control input. dcb selects dc-balanced, non-dc-balanced, or reserved operation (see table 1). 8 rxin0- inverting channel 0 lvds serial-data input 9 rxin0+ noninverting channel 0 lvds serial-data input 10 rxin1- inverting channel 1 lvds serial-data input 11 rxin1+ noninverting channel 1 lvds serial-data input 12 lvdsv cc lvds supply voltage. bypass lvdsv cc to gnd with 0.1? and 0.001? capacitors in parallel as close to the pin as possible. 13, 18 lvdsgnd lvds ground 14 rxin2- inverting channel 2 lvds serial-data input 15 rxin2+ noninverting channel 2 lvds serial-data input 16 rxclkin- inverting lvds parallel-rate clock input 17 rxclkin+ noninverting lvds parallel-rate clock input 19, 21 pllgnd pll ground 20 pllv cc pll supply voltage. bypass pllv cc to gnd with 0.1? and 0.001? capacitors in parallel as close to the pin as possible. 22 pwrdwn 5v-tolerant lvttl/lvcmos power-down input. pwrdwn is internally pulled down to gnd. outputs are high impedance when pwrdwn = low or open. 23 rxclkout p ar al l el - rate c l ock s i ng l e- e nd ed o utp ut. the m ax 9242 has a r i si ng - ed g e str ob e. the m ax 9244/m ax 9246/ m ax 9254 have a fal l i ng - ed g e str ob e. 24 rxout0 26 rxout1 27 rxout2 channel 0 single-ended outputs 28, 36, 48 v cco output supply voltage. bypass each v cco to gnd with 0.1? and 0.001? capacitors in parallel as close to the pin as possible. 29 rxout3 30 rxout4 31 rxout5 33 rxout6 channel 0 single-ended outputs
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance 12 ______________________________________________________________________________________ max9242 max9244 max9246 max9254 rxin0+ rxin0- rxin1+ rxin1- rxin2+ rxin2- rxclkin+ rxclkin- dcb rxout0?xout6 rxout7?xout13 rxout14?xout20 rxclkout ssg serial-to-parallel channel 0 7 7 serial-to-parallel channel 1 7 7 serial-to-parallel channel 2 7 7 fifo pll1 7x or 9x strobes fifo control spread- spectrum pll (sspll) clk in clk out parallel clock pwrdwn functional diagram pin description (continued) pin name function 34 rxout7 35 rxout8 37 rxout9 39 rxout10 40 rxout11 41 rxout12 channel 1 single-ended outputs 42 v cc digital supply voltage. bypass v cc to gnd with 0.1? and 0.001? capacitors in parallel as close to the pin as possible. 43 rxout13 channel 1 single-ended output 45 rxout14 46 rxout15 47 rxout16 channel 2 single-ended outputs
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance ______________________________________________________________________________________ 13 detailed description the max9242/max9244/max9246/max9254 deserialize three lvds serial-data inputs into 21 single-ended lvc- mos/lvttl outputs. the outputs are programmable for no spread or for a spread of ?% or ?%, relative to the lvds input clock frequency. the max9242/max9244/ max9254 operate at a parallel clock frequency of 16mhz to 34mhz in dc-balanced mode and 20mhz to 40mhz in non-dc-balanced mode. the max9246 operates at a 6mhz-to-18mhz parallel clock frequency in dc-balanced mode and 8mhz-to-20mhz parallel clock frequency in non-dc-balanced mode. dc-balanced or non-dc-bal- anced operation is controlled by the dcb input. the max9242 has a rising-edge strobe and the max9244/ max9246/max9254 have a falling-edge strobe. dc balance (dcb) dc-balanced or non-dc-balanced operation is con- trolled by the dcb input (see table 1). in the non-dc- balanced mode, each channel deserializes 7 bits every cycle of the parallel clock. in dc-balanced mode, 9 bits are deserialized every clock cycle (7 data bits + 2 dc-balanced bits). the highest serial-data rate on each channel in dc-balanced mode is 34mhz x 9 = 306mbps. in non-dc-balanced mode, the maximum data rate is 40mhz x 7 = 280mbps. data coding by the max9209/max9213 serializers (that are companion devices to the max9242/max9244/ max9246/m ax9254 deserializers) limits the imbalance of ones and zeros transmitted on each channel. if +1 is assigned to each binary 1 transmitted and -1 is assigned to each binary 0 transmitted, the variation in the running sum of assigned values is called the digital sum variation (dsv). the maximum dsv for the data channels is 10. at most, 10 more zeros than ones, or 10 more ones than zeros, are ever transmitted. the maxi- mum dsv for the clock channel is 5. limiting the dsv and choosing the correct coupling capacitors maintain differential signal amplitude and reduces jitter due to droop on ac-coupled links. to obtain dc balance on the data channels, the serial- izer parallel data is inverted or not inverted, depending on the sign of the digital sum at the word boundary. two complementary bits are appended to each group of 7 parallel-input data bits to indicate to the max9242/ max9244/max9246 /max9254 deserializer whether the data bits are inverted (see figures 11 and 12). the deserializer restores the original state of the parallel data. the lvds clock signal alternates duty cycles of 4/9 and 5/9 to maintain dc balance. spread-spectrum generator (ssg) the max9242/max9244/max9246/max9254 single- ended data and clock outputs are programmable for a variation of ?% or ?% around the lvds input clock fre- quency. the modulation rate of the frequency variation is 32.48khz for a 33mhz lvds clock input and scales lin- early with the input clock frequency (see table 2). the spread spectrum can also be turned off. the output spread is controlled through the ssg input (see table 3). table 1. dcb function dcb input level function high non-dc-balanced mode mid reserved low dc-balanced mode txin_ is data from the serializer. txin1 txin7 txin8 txin14 txin15 + - cycle n + 1 cycle n cycle n - 1 txin2 txin6 txin3 txin4 txin5 txin9 txin13 txin10 txin11 txin12 txin0 txin1 txin2 txin6 txin3 txin4 txin5 txin7 txin8 txin9 txin13 txin10 txin11 txin12 txin14 txin15 txin16 txin20 txin17 txin18 txin19 txin0 txin1 txin7 txin8 txin14 txin15 txin16 txin20 txin17 txin18 txin19 txin0 rxclkin_ rxin1_ rxin0_ rxin2_ figure 11. deserializer serial input in non-dc-balanced mode
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance to select the mid level, leave the input open, or if driven, put the driver output in high impedance. the driver high- impedance leakage current must be less than ?0?. any spread change causes a maximum delay time of 32,800 x rcip before output data is valid. when the spread amount is changed from ?% to ?% or vice- versa, the data outputs go low for one delay time (see figure 13). similarly, when the spread is changed from no spread to ?% or ?%, the data outputs go low for one delay time (see figure 14). the data outputs contin- ue to switch but are not valid when the spread amount is changed from ?% or ?% to no spread (see figure 15). the spread-spectrum function is also available when the max9242/max9244/max9246 /max9254 oper- ate in non-dc-balanced mode. hot swap when the max9242/max9244/max9246/max9254 are connected to an active serializer, they synchronize correct- ly. the pll control voltage does not saturate in response to high-frequency glitches that may occur during a hot swap. the pwrdwn input on the max9242/max9244/max9246/ max9254 does not need to be cycled when these devices are connected to an active serializer. pll lock time the max9242/max9244/max9246 /max9254 use two plls. the first pll (pll1) generates a 7x clock (non-dc- balanced mode) or a 9x clock (dc-balanced mode) from rxclkin_ for deserializing the lvds inputs. the second pll (sspll) is used for spread-spectrum modulation. during initial power-up, the pll1 locks, and sspll locks immediately after. the pll lock times are set by an inter- nal counter. the maximum time to lock for each pll is 32,800 clock periods. power and clock should be stable to meet the lock time specification. after initialization, if the first pll loses lock, it locks again and then the txin_, dca_, and dcb_ are data from the serializer. dca0 dcb1 dca1 dcb2 dca2 cycle n + 1 cycle n cycle n - 1 txin2 txin6 txin3 txin4 txin5 txin9 txin13 txin10 txin11 txin12 txin2 txin3 txin4 dca0 txin5 txin6 dcb0 txin9 txin10 txin11 dca1 txin12 txin13 dcb1 txin16 txin17 txin18 dca2 txin19 txin20 dcb2 txin0 txin1 txin7 txin8 txin14 txin15 txin16 txin20 txin17 txin18 txin19 dcb0 rxclkin_ rxin1_ rxin0_ rxin2_ txin1 txin8 txin15 txin0 txin7 txin14 + - figure 12. deserializer serial input in dc-balanced mode table 2. modulation rate f rxclkin_ (mhz) f m (khz) = f rxclkin _ / 1016 6 5.91 8 7.87 10 9.84 16 15.75 18 17.72 20 19.68 33 32.48 34 33.46 40 39.37 table 3. ssg function ssg input level function high rxclkout frequency spread ?% relative to rxclkin_ mid rxclkout frequency spread ?% relative to rxclkin_ low no spread on rxclkout relative to rxclkin_ note: rxout_ data outputs are spread because rxclkout strobes the output of the fifo. 14 ______________________________________________________________________________________
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance ______________________________________________________________________________________ 15 spread-spectrum pll locks immediately after (see figure 16). if the spread-spectrum pll loses lock, it locks again with only one pll lock delay (see figure 17). ac-coupling benefits bit errors experienced with dc-coupling (figure 18) can be eliminated by increasing the receiver common- mode voltage range through ac-coupling. ac-coupling increases the common-mode voltage range of an lvds receiver to nearly the voltage rating of the capacitor. the typical lvds driver output is 350mv centered on a 1.25v offset voltage, making single-ended output voltages of 1.425v and 1.075v. an lvds receiver accepts signals from 0v to 2.4v, allowing approximately 1v common- mode difference between the driver and receiver on a rplls2 (32,800 x rcip) 2% or 4% spread 4% or 2% spread low ssg rxclkout rxout_ figure 13. output waveforms when spread amount is changed rplls2 (32,800 x rcip) 2% or 4% spread low no spread ssg rxclkout rxout_ figure 14. output waveforms when spread is added rplls2 (32,800 x rcip) no spread 4% or 2% spread ssg rxclkout rxout_ data switching but not valid figure 15. output waveforms when spread is removed
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance 16 ______________________________________________________________________________________ dc-coupled link (2.4v - 1.425v = 0.975v and 1.075v - 0v = 1.075v). common-mode voltage differences may be due to ground potential variation or common-mode noise. if there is more than 1v of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. ac-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. a common-mode voltage differ- ence up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. dc-bal- anced coding of the data is required to maintain the differential signal amplitude and limit jitter on an ac-coupled link. a capacitor in series with each output of the lvds driver is sufficient for ac-coupling. however, two capacitors?ne at the serializer output and one at the deserializer input?rovide protection in case either end of the cable is shorted to a high voltage. applications information selection of ac-coupling capacitors voltage droop and the dsv of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the lvds receiver termination resistor (r t ), the lvds driver output resistor (r o ), and the series ac-coupling capac- itors (c). the rc time constant for two equal-value series capacitors is (c x (r t + r o )) / 2 (figure 19). the rc time constant for four equal-value series capacitors is (c x (r t + r o )) / 4 (figure 20). rplls (65,600 x rcip) low low rxclkout internal pll1 lock internal sspll lock rxout_ low low figure 16. output waveforms when pll1 loses lock and locks again rplls2 (32,800 x rcip) low internal sspll lock rxclkout rxout_ timing shown for stable clock and data inputs figure 17. output waveforms if spread-spectrum pll loses lock and locks again
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance ______________________________________________________________________________________ 17 r t is required to match the transmission line impedance (usually 100 ) and r o is determined by the lvds dri- ver design (the minimum differential output resistance of 78 for the max9209/max9213 serializers is used in the following example). this condition leaves the capac- itor selection to change the system time constant. in the following example, the capacitor value for a 2% droop is calculated. jitter due to this droop is then cal- culated assuming a 1ns transition time: c = -(2 x t b x dsv) / (ln (1 - d) x (r t + r o )) (eq 1) where: c = ac-coupling capacitor (f) t b = bit time (s) dsv = digital sum variation (integer) ln = natural log d = droop (% of signal amplitude) r t = termination resistor ( ) r o = output resistance ( ) equation 1 is for two series capacitors (figure 19). the bit time (t b ) is the period of the parallel clock divided by 9. the dsv is 10. see equation 3 for four series capacitors (figure 20). the capacitor for 2% maximum droop at 16mhz parallel rate clock is: c = -(2 x t b x dsv) / (ln (1 - d) x (r t + r o )) c = -(2 x 6.95ns x 10) / (ln (1 - 0.02) x (100 + 78 )) c = 0.038? jitter due to droop is proportional to the droop and transition time: t j = t t x d (eq 2) where: t j = jitter (s) t t = transition time (s) (0 to 100%) d = droop (% of signal amplitude) jitter due to 2% droop and assumed 1ns transition time is: t j = 1ns x 0.02 t j = 20ps the transition time in a real system depends on the fre- quency response of the cable driven by the serializer. figure 18. dc-coupled link, non-dc-balanced mode 7:1 1:7 fifo 7 7 100 7:1 1:7 fifo 7 7 100 7:1 1:7 fifo 7 7 100 pll pll1 + sspll 100 max9209/max9213 max9242/max9244/max9246/max9254 txout txclk out rxin__ rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout_ pwrdwn txclk in txin transmission line r o r t
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance 18 ______________________________________________________________________________________ the capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and jitter. use high-frequency, surface-mount ceramic capacitors. equation 1 altered for four series capacitors (figure 20) is: c = -(4 x t b x dsv) / (ln (1 - d) x (r t + r o )) (eq 3) fail-safe the max9242/max9244/max9246/max9254 have fail- safe lvds inputs in non-dc-balanced mode (figure 1). fail-safe drives the outputs low when the corresponding lvds input is open, undriven and shorted, or undriven and parallel terminated. the fail-safe on the lvds clock input drives all outputs low when power is stable. fail- safe does not operate in dc-balanced mode. input bias and frequency detection in dc-balanced mode, the inverting and noninverting lvds inputs are internally connected to +1.2v through 42k (min) to provide biasing for ac-coupling (figure 1). to prevent switching due to noise when the clock input is not driven, bias the clock inputs (rxclkin+, rxclkin-) to differential +15mv by connecting a 10k ?% pullup resistor between the noninverting input and lvdsv cc , and a 10k ?% pulldown resistor between the inverting input and ground. these bias resistors, along with the 100 ?% tolerant termination resistor, provide +15mv of differential input. the +15mv bias causes some small degradation of rskm proportional to the slew rate of the clock input. for example, if the clock transitions 250mv in 500ps, the slew rate of 0.5mv/ps reduces rskm by 30ps. unused lvds data inputs in non-dc-balanced mode, leave unused lvds data inputs open. in non-dc-balanced mode, the input fail- safe circuit drives the corresponding outputs low, and no pullup or pulldown resistors are needed. in dc-balanced mode, at each unused lvds data input, pull the inverting input up to lvdsv cc using a 10k resistor, and pull the noninverting input down to ground using a 10k resistor. do not connect a termination resistor. the pullup and pulldown resistors drive the corresponding outputs low and prevent switching due to noise. (7 + 2):1 7 7 100 (7 + 2):1 7 7 100 (7 + 2):1 1:(9 - 2) + fifo 1:(9 - 2) + fifo 1:(9 - 2) + fifo 7 7 100 pll 100 max9209/max9213 max9242/max9244/max9246/max9254 txout txclk out rxin__ rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout_ pwrdwn txclk in txin high-frequency, ceramic surface-mount capacitors can also be placed at the serializer instead of the deserializer. pll1 + sspll r o r t figure 19. two capacitors per link, ac-coupled, dc-balanced mode
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance ______________________________________________________________________________________ 19 link power-up sequence the recommended link power-up sequence is to power up the serializer, wait until the serializer pll locks, and then power up the deserializer. this sequence prevents the deserializer from seeing an undriven or unstable input when powering up. pwrdwn driving pwrdwn low puts the outputs in high imped- ance, stops the pll, and reduces supply current to 50? or less. driving pwrdwn high drives the outputs low until the pll locks. the outputs of two deserializers can be bused to form a 2:1 mux with the outputs con- trolled by pwrdwn . wait 100ns between disabling one deserializer (driving pwrdwn low) and enabling the second one (driving pwrdwn high) to avoid con- tention of the bused outputs. power-supply bypassing there are separate on-chip power domains for digital circuits, outputs, pll, and lvds inputs. bypass each v cc , v cco , pllv cc , and lvdsv cc with high-frequency, surface-mount ceramic 0.1? and 0.001? capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. cables and connectors interconnect for lvds typically has a differential imped- ance of 100 . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic field cancel- ing effects. balanced cables pick up noise as common mode, which is rejected by the lvds receiver. board layout keep the lvttl/lvcmos outputs and lvds input sig- nals separated to prevent crosstalk. a four-layer pc board with separate layers for power, ground, lvds inputs, and digital signals is recommended. layout pc board traces for 100 differential characteristic imped- ance. the trace dimensions depend on the type of (7 + 2):1 7 7 100 (7 + 2):1 7 7 100 (7 + 2):1 7 7 100 pll 100 max9209/max9213 max9242/max9244/max9246/max9254 txout txclk out rxin__ rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout_ pwrdwn txclk in txin high-frequency ceramic surface-mount capacitors pll1 + sspll 1:(9 - 2) + fifo 1:(9 - 2) + fifo 1:(9 - 2) + fifo r o r t figure 20. four capacitors per link, ac-coupled, dc-balanced mode
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance 20 ______________________________________________________________________________________ trace used (microstrip or stripline). note that two 50 pc board traces do not have 100 differential imped- ance when brought close together?he impedance goes down when the traces are brought closer. route the pc board traces for an lvds channel (there are two conductors per lvds channel) in parallel to maintain the differential characteristic impedance. place the termination resistor at the end of the pc board traces within a 1/4 inch of the lvds receiver input. avoid vias. if vias must be used, use only one pair per lvds channel and place the via for each line at the same point along the length of the pc board traces. this way, any reflections will occur at the same time. do not make vias into test points for ate. make lvds clock and data pairs the same length on the pc board to avoid pair-to-pair skew. make the pc board traces that make up a differential pair the same length to avoid skew within the differential pair. 5v-tolerant input pwrdwn is 5v tolerant and is internally pulled down to gnd. ssg and dcb are not 5v tolerant. the input voltage range for ssg and dcb is nominally ground to v cc . skew margin (rskm) skew margin (rskm) is the time allowed for degrada- tion of the serial-data sampling setup and hold times by sources other than the deserializer. the deserializer sampling uncertainty is accounted for and does not need to be subtracted from rskm. the main outside contributors of jitter and skew that subtract from rskm are interconnect intersymbol interference, serializer pulse position uncertainty, and pair-to-pair path skew. v cco output supply and power dissipation the outputs have a separate supply (v cco ) for interfacing to systems with 1.8v to 5v nominal input logic levels. the dc electrical characteristics table gives the maximum supply current for v cco = 3.6v with 8pf load at several switching frequencies with all outputs switching in the worst-case switching pattern. the approximate incremen- tal supply current for v cco other than 3.6v with the same 8pf load and worst-case pattern can be calculated using: i i = c t v i 0.5f c x 21 (data outputs) + c t v i f c x 1 (clock output) where: i i = incremental supply current c t = total internal (c int ) and external (c l ) load capaci- tance v i = incremental supply voltage f c = output clock switching frequency the incremental current is added to (for v cco > 3.6v) or subtracted from (for v cco < 3.6v) the dc electrical characteristics table maximum supply current. the internal output buffer capacitance is c int = 6pf. the worst-case pattern switching frequency of the data out- puts is half the switching frequency of the output clock. in the following example, the incremental supply current of the max9244 in spread and dc-balanced mode is cal- culated for v cco = 5.5v, f c = 34mhz, and c l = 8pf: v i = 5.5v - 3.6v = 1.9v c t = c int + c l = 6pf + 8pf = 14pf where: i i = c t v i 0.5f c x 21 (data outputs) + c t v i f c x 1 (clock output) i i = (14pf x 1.9v x 0.5 x 34mhz x 21) + (14pf x 1.9v x 34mhz) i i = 9.5ma + 0.9ma = 10.4ma. the maximum supply current in dc-balanced mode for v cc = v cco = 3.6v at f c = 34mhz is 125ma (from the dc electrical characteristics table). add 10.4ma to get the total approximate maximum supply current at v cco = 5.5v and v cc = 3.6v. if the output supply voltage is less than v cco = 3.6v, the reduced supply current can be calculated using the same formula and method. at high switching frequency, high supply voltage, and high capacitive loading, power dissipation can exceed the package power dissipation rating. do not exceed the maximum package power dissipation rating. see the absolute maximum ratings for maximum package power dissipation capacity and temperature derating. rising- or falling-edge output strobe the max9242 has a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of rxclkout . the max9244/max9246/ max9254 have a falling-edge output strobe, which latches the parallel output data into the next chip on the falling edge of rxclkout. the deserializer output strobe polarity does not need to match the serializer input strobe polarity. three-level logic inputs ssg and dcb (dcb mid level is reserved) are three- level-logic inputs. a logic-high input voltage must be greater than +2.5v and a logic-low input voltage must be less than +0.8v. a mid-level logic is recognized by the max9242/max9244/max9246/max9254 when the input is left open or connected to a driver in a high- impedance state. a weak inverter on the input stage of
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance ______________________________________________________________________________________ 21 ssg and dcb provides the proper mid-level voltage under conditions of low input current. the mid-level input current must not be greater than ?0?, and the mid-level logic state cannot be driven with an external voltage source. iec 61000-4-2 level 4 and iso 10605 esd protection the max9242/max9244/max9246/max9254 esd toler- ance is rated for human body model, iec 61000-4-2 and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic sys- tems. all lvds inputs on the max9242/max9244/ max9246/max9254 meet iso 10605 esd protection at ?0kv air-gap discharge and ?kv contact discharge and iec 61000-4-2 esd protection at ?5kv air-gap discharge and ?kv contact discharge. all other pins meet the human body model esd tolerance of ?.5kv. the human body model discharge components are c s = 100pf and r d = 1.5k (figure 21). the iec 61000-4- 2 discharge components are c s = 150pf and r d = 330 (see figure 22). the iso 10605 discharge com- ponents are c s = 330pf and r d = 2k (figure 23). storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 1.5k c s 100pf figure 21. human body esd test circuit c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r2 330 figure 22. iec 61000-4-2 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2k c s 330pf figure 23. iso 10605 contact discharge esd test circuit 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 v cco rxout16 rxout15 rxout14 rxout19 gnd rxout18 rxout17 top view max9242 max9244 max9246 max9254 gnd rxout13 v cc rxout12 rxin0- dcb ssg rxout20 rxout11 rxout10 rxin1- rxin0+ 38 37 36 35 34 33 32 31 30 29 gnd rxout9 v cco rxout8 rxout7 rxout6 gnd rxout5 rxout4 rxout3 11 12 13 14 15 16 17 18 19 rxin2- lvdsgnd lvdsv cc rxin1+ lvdsgnd rxclkin+ rxclkin- rxin2+ pllv cc pllgnd pllgnd tssop 20 21 rxout0 24 28 25 v cco 22 27 23 rxclkout 26 rxout1 rxout2 gnd pwrdwn pin configuration chip information process: cmos
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance 22 ______________________________________________________________________________________ ordering information (continued) part temp range pin-package max9246 eum -40? to +85? 48 tssop max9246eum/v+ -40? to +85? 48 tssop max9246gum -40? to +105? 48 tssop max9246gum/v+ -40? to +105? 48 tssop max9254 eum -40? to +85? 48 tssop max9254eum/v+ -40? to +85? 48 tssop + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. note: all devices are available in lead(pb)-free/rohs-compliant packaging. specify lead(pb)-free/rohs compliant by adding a + symbol at the end of the part number when ordering. package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package draw- ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code document no. 48 tssop u48-1 21-0155
max9242/max9244/max9246/max9254 21-bit deserializers with programmable spread spectrum and dc balance maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 23 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 3 2/09 supply currents measured before the deserializers were fully locked to incoming serial data. dc electrical characteristic s updated 2, 3 4 7/09 added automotive qualified parts to ordering information table 1

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